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E2L0017-17-Y1
Semiconductor MSM548263
Semiconductor 262,144-Word 8-Bit Multiport DRAM
This version: Jan. 1998 MSM548263 Previous version: Dec. 1996
DESCRIPTION
The MSM548263 is a 2-Mbit CMOS multiport DRAM composed of a 262,144-word by 8-bit dynamic RAM, and a 512-word by 8-bit SAM. Its RAM and SAM operate independently and asynchronously. It supports three types of operations: random access to RAM port, high speed serial access to SAM port, and bidirectional transfer of data between any selected row in the RAM port and the SAM port. In addition to the conventional multiport DRAM operating modes, the MSM548263 features block write, flash write functions and extended page mode on the RAM port and a split data transfer capability, programmable stops on the SAM port. The SAM port requires no refresh operation because it uses static CMOS flip-flops.
FEATURES
* Single power supply: 5 V 10% * RAS only refresh * Full TTL compatibility * CAS before RAS refresh * Multiport organization * Hidden refresh RAM : 256K word 8 bits * Serial read/write SAM : 512 word 8 bits * 512 tap location * Extended page mode * Programmable stops * Write per bit * Bidirectional data transfer * Persistent write per bit * Split transfer * Masked flash write * Masked write transfer * Masked block write * Refresh: 512 cycles/8 ms * Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM548263-xxJS) 44/40-pin 400 mil plastic TSOP (Type II)(TSOPII44/40-P-400-0.80-K)(Product : MSM548263-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM548263-60 MSM548263-70 MSM548263-80 Access Time RAM 60 ns 70 ns 80 ns SAM 17 ns 17 ns 20 ns Cycle Time RAM 120 ns 140 ns 150 ns SAM 22 ns 22 ns 25 ns Power Dissipation Operating 140 mA 130 mA 120 mA Standby 8 mA 8 mA 8 mA
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Semiconductor
MSM548263
PIN CONFIGURATION (TOP VIEW)
VCC
1 2 3 4 5 6 7 8 9 10 11 40 39
VSS
SC
SDQ8 SDQ7 SDQ6 SDQ5 SE DQ8 DQ7 DQ6 DQ5 VSS DSF NC CAS QSF A0 A1 A2 A3 VSS
SDQ1 SDQ2 SDQ3 SDQ4 TRG DQ1 DQ2 DQ3 DQ4 WE
38 37 36 35 34 33 32 31
VCC SC SDQ1 SDQ2 SDQ3 SDQ4 TRG DQ1 DQ2 DQ3
1 2 3 4 5 6 7 8 9 10
44 43 42 41 40 39 38 37 36 35
VSS SDQ8 SDQ7 SDQ6 SDQ5 SE DQ8 DQ7 DQ6 DQ5
30 29 28 27 26 25 24 23 22 21
VSS 12
13 14 15 16 17 18 19 20
RAS A8 A7 A6 A5 A4 VCC
DQ4 VSS WE RAS A8 A7 A6 A5 A4 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
VSS DSF NC CAS QSF A0 A1 A2 A3 VSS
44/40-Pin Plastic TSOP (II) (K Type)
40-Pin Plastic SOJ
Pin Name A0 - A8 DQ1 - DQ8 SDQ1 - SDQ8 RAS CAS WE TRG
Function Address Input RAM Inputs/Outputs SAM Inputs/Outputs Row Address Strobe Column Address Strobe Write Enable Transfer/Output Enable
Pin Name SC SE DSF QSF VCC VSS NC
Function Serial Clock SAM Port Enable Special Function Input Special Function Output Power Supply (5 V) Ground (0 V) No Connection
Note:
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
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BLOCK DIAGRAM
Semiconductor
Column Address Buffer
Column Decoder
Block Write Control I/O Control
Column Mask Register Color Register Mask Register RAM Input Buffer DQ 1 - 8 RAM Output Buffer
Sense Amp.
Row Decoder
Row Address Buffer
512 512 8 RAM ARRAY
Flash Write Control SAM Input Buffer SDQ 1 - 8 SAM Output Buffer Timing Generator
A0 - A8
Refresh Counter
Gate SAM
Gate SAM
RAS CAS TRG WE DSF SC SE
Serial Decoder SAM Address Buffer
SAM Address Counter
QSF
SAM Stop Control
VCC
MSM548263
VSS
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Semiconductor
MSM548263
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Note: 1) Parameter Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C -- -- Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
Recommended Operating Conditions
(Ta = 0C to 70C) (Note: 2) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min. 4.5 2.4 -1.0 Typ. 5.0 -- -- Max. 5.5 6.5 0.8 Unit V V V
Capacitance
(VCC = 5 V 10%, f = 1 MHz, Ta = 25C) Parameter Input Capacitance Input/Output Capacitance Output Capacitance Symbol Ci Cio Co(QSF) Min. -- -- -- Max. 8 9 9 Unit pF pF pF
Note:
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter Output "H" Level Voltage Output "L" Level Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -1 mA IOL = 2.1 mA 0 VIN VCC All other pins not under test = 0 V 0 VOUT 5.5 V Output Disable Min. 2.4 -- -10 Max. -- 0.4 10 mA -10 10 Unit V
Output Leakage Current
ILO
4/40
Semiconductor DC Characteristics 2
MSM548263
(VCC = 5 V 10%, Ta = 0C to 70C) Item (RAM) Operating Current (RAS, CAS Cycling, tRC = tRC min.) Standby Current (RAS, CAS = VIH) RAS Only Refresh Current (RAS Cycling, CAS = VIH, tRC = tRC min.) Page Mode Current (RAS = VIL, CAS Cycling, tPC = tPC min.) CAS before RAS Refresh Current (RAS Cycling, CAS before RAS, tRC = tRC min.) Data Transfer Current (RAS, CAS Cycling, tRC = tRC min.) Flash Write Current (RAS, CAS Cycling, tRC = tRC min.) Block Write Current (RAS, CAS Cycling, tRC = tRC min.) SAM Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active Symbol ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A ICC6 ICC6A ICC7 ICC7A ICC8 ICC8A -60 95 140 8 60 95 140 75 140 95 140 95 140 95 140 95 140 -70 85 130 8 55 85 130 70 130 85 130 85 130 85 130 85 130 -80 75 120 8 50 75 120 65 120 75 120 75 120 75 120 75 120 mA 3, 4 3, 4 17 3, 4 18 3, 4 3, 4 3, 4 17 3, 4 3, 4 3, 4 3, 4 Max. Max. Max. Unit Note 3, 4 17
5/40
Semiconductor AC Characteristics (1/3)
-60 120 170 40 85 -- -- -- -- 0 3 50 60 60 15 60 15 20 15 30 10 10 0 10 0 10 50 0 0 0 0 0 5 0 10 50 10 15 15 -- -- -- -- 60 30 15 35 15 35 -- 10k 100k -- -- 10k 45 30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -70 140 185 45 90 -- -- -- -- 0 3 60 70 70 20 70 20 20 15 35 10 10 0 10 0 10 55 0 0 0 0 0 5 0 12 55 12 20 20 -- -- -- -- 70 35 20 40 20 35 -- 10k 100k -- -- 10k 50 35 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -80 150 195 50 90 -- -- -- -- 0 3 60 80 80 25 80 25 20 15 40 10 10 0 10 0 12 55 0 0 0 0 0 5 0 15 55 15 20 20
MSM548263
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS Access Time from CAS Precharge Output Buffer Turn-off Delay Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode Only) RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to RAS Precharge Time CAS Precharge Time (Fast Page Mode) Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time referenced to RAS Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS CAS "H" to RAS "H" Lead Time RAS "H" to CAS "H" Lead Time Data Output Hold after CAS Low Write Command Set-up Time Write Command Hold Time Write Command Hold Time referenced to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time
Symbol tRC tRWC tPC tPRWC tRAC tAA tCAC tCPA tOFF tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tRAL tCRP tCP tASR tRAH tASC tCAH tAR tRCS tRCH tRRH tCRL tRCL tCOH tWCS tWCH tWCR tWP tRWL tCWL
Min. Max. Min. Max. Min. Max. -- -- -- -- 80 40 25 45 20 35 -- 10k 100k -- -- 10k 55 40 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 13 11 11 14 14 8, 14 8, 14 8, 15 8, 15 10 7
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Semiconductor AC Characteristics (2/3)
-60 0 10 50 80 50 35 0 0 -- 0 10 10 10 10 0 -- 0 10 0 10 50 0 10 0 10 0 10 0 10 50 20 15 50 20 60 40 20 5 -- -- -- -- -- -- -- -- 15 10 -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- -- 0 12 55 90 55 40 0 0 -- 0 10 15 10 10 0 -- 0 10 0 10 55 0 10 0 10 0 10 0 10 60 25 20 60 20 70 45 20 5 -70 -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- -- 0 15 55 100 65 45 0 0 -- 0 10 15 10 10 0 -- 0 12 0 12 55 0 12 0 12 0 12 0 12 65 30 25 60 20 80 45 25 5 -80
MSM548263
Parameter Data Set-up Time Data Hold Time Data Hold Time referenced to RAS RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Data to CAS Delay Time Data to TRG Delay Time Access Time from TRG Output Buffer Turn-off Delay from TRG TRG Command Hold Time RAS Hold Time referenced to TRG CAS Set-up Time for CAS before RAS Cycle CAS Hold Time for CAS before RAS Cycle RAS Precharge to CAS Active Time Refresh Period WE Set-up Time WE Hold Time DSF Set-up Time referenced to RAS DSF Hold Time referenced to RAS (1) DSF Hold Time referenced to RAS (2) DSF Set-up Time referenced to CAS DSF Hold Time referenced to CAS Write Per Bit Mask Data Set-up Time Write Per Bit Mask Data Hold Time TRG High Set-up Time TRG High Hold Time TRG Low Set-up Time TRG Low Hold Time TRG Low Hold Time referenced to RAS TRG Low Hold Time referenced to Column Address TRG Low Hold Time referenced to CAS TRG to RAS Precharge Time TRG Precharge Time RAS to First SC Delay Time (Read Transfer) Column Address to First SC Delay Time CAS to First SC Delay Time (Read Transfer) Last SC to TRG Lead Time
Symbol tDS tDH tDHR tRWD tAWD tCWD tDZC tDZO tOEA tOEZ tOEH tROH tCSR tCHR tRPC tREF tWSR tRWH tFSR tRFH tFHR tFSC tCFH tMS tMH tTHS tTHH tTLS tTLH tRTH tATH tCTH tTRP tTP tRSD tASD tCSD tTSL
Min. Max. Min. Max. Min. Max. -- -- -- -- -- -- -- -- 20 10 -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- 10k 10k -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 13 12 12
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Semiconductor AC Characteristics (3/3)
-60 15 20 10 22 5 5 -- 5 -- 10 10 0 25 25 -- -- -- -- 30 0 10 0 0 0 10 0 10 -- -- 30 -- -- -- 17 -- 17 -- -- 20 -- -- 25 25 30 70 -- -- -- -- -- -- -- -- -- 15 25 10 22 5 5 -- 5 -- 10 10 0 25 25 -- -- -- -- 40 0 10 0 0 0 10 0 10 -70 -- -- 40 -- -- -- 17 -- 17 -- -- 20 -- -- 25 25 35 75 -- -- -- -- -- -- -- -- -- 15 25 10 25 7 7 -- 5 -- 10 10 0 30 30 -- -- -- -- 40 0 12 0 0 0 12 0 12 -80
MSM548263
Parameter TRG to First SC Delay Time (Read Transfer) Last SC to RAS Set-up Time (Serial Input) Serial Output Buffer Turn-off Delay from RAS SC Cycle Time SC Pulse Width (SC High Time) SC Precharge Time (SC Low Time) Access Time from SC Serial Output Hold Time from SC Access Time from SE SE Pulse Width SE Precharge Time Serial Output Buffer Turn-off Delay from SE Split Transfer Set-up Time Split Transfer Hold Time SC-QSF Delay Time TRG-QSF Delay Time CAS-QSF Delay Time RAS-QSF Delay Time RAS to Serial Input Delay Time Serial Input Set-up Time Serial Input Hold Time Serial Input to SE Delay Time Serial Input to First SC Delay Time Serial Write Enable Set-up Time Serial Write Enable Hold Time Serial Write Disable Set-up Time Serial Write Disable Hold Time
Symbol tTSD tSRS tSDZ tSCC tSC tSCP tSCA tSOH tSEA tSE tSEP tSEZ tSTS tSTH tSQD tTQD tCQD tRQD tSDD tSDS tSDH tSZE tSZS tSWS tSWH tSWIS tSWIH
Min. Max. Min. Max. Min. Max. -- -- 40 -- -- -- 20 -- 20 -- -- 20 -- -- 25 25 35 75 -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 9 19 9 10
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Semiconductor Notes:
MSM548263
1. Exposure beyond the "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate. 4. These parameters depend on output loading. Specified values are obtained with the output open. 5. An initial pause of 200 ms is required after power up followed by any 8 RAS cycles (TRG = "high") and any 8 SC cycles before proper device operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. RAM port outputs are measured with a load equivalent to 1 TTL load and 50 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V. 9. SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V. 10. tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) define the time at which the outputs achieve the open circuit condition, and are not referenced to output voltage levels. This parameter is sampled and not 100% tested. 11. Either tRCH or tRRH must be satisfied for a read cycle. 12. These parameters are referenced to CAS leading edge of early write cycles, and to WE leading edge in TRG controlled write cycles and read modify write cycles. 13. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit throughout the entire cycle; If tRWD tRWD (Min.), tCWD tCWD (Min.) and tAWD tAWD (Min.), the cycle is a read modify write cycle, and the data out will contain data read from the selected cell; If neither of the above sets of conditions are satisfied, the condition of the data out is indeterminate. 14. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 15. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 16. Input levels at the AC testing are 3.0 V/0 V. 17. Address (A0 - A8) may be changed two times or less while RAS = VIL. 18. Address (A0 - A8) may be changed once or less while CAS = VIH and RAS = VIL. 19. This is guaranteed by design. (tSOH/tCOH = tSCA/tCAC - output transition time) This parameter is not 100% tested.
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Semiconductor
MSM548263
TIMING WAVEFORM
Read Cycle (Outputs Controlled by RAS)
tRC tRAS RAS tRP
CAS
Address
DSF
WE
DQ1 - 8
TRG
, ,, ,,
tCSH tCRP tRCD tRSH tCAS tAR tRAD tCRL tRAL tASR tRAH tASC tCAH Row Column tFHR tFSR tRFH tFSC tCFH tRCS tRCH tRRH tCAC tRAC tOFF tAA Open Valid Data tROH tTHS tTHH tOEA tOEZ "H" or "L"
10/40
Semiconductor Read Cycle (Outputs Controlled by CAS)
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
, ,, ,,
tCSH tCRP tRCD tRSH tCAS tAR tRAD tRCL tRAL tASR tRAH tASC tCAH Row Column tFHR tFSR tRFH tFSC tCFH tRCH tRCS tRRH tCAC tRAC tOFF tAA Open Valid Data tROH tTHS tTHH tOEA tOEZ "H" or "L"
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Semiconductor Extended Page Mode Read Cycle
MSM548263
,,, ,
tRASP tRP RAS tCSH tPC tRSH tCRP tRCD tCAS tCP tCAS tCP tCAS CAS tAR tRAD tRAL tASR tRAH tASC tCAH tASC tCAH tASC tCAH Address Row Column Column Column tFHR tFSR tRFH tFSC tCFH tFSC tCFH tFSC tCFH DSF tRCS tRCS tRCH tRCS tRCH tRCH tRRH WE tCAC tCAC tCAC tAA tCOH tCOH tOFF DQ1 - 8 Open Valid Data tRAC
Valid Data Valid Data
Valid Data
tAA tCPA
tTHS
tTHH
tOEA
tOEZ
tAA tCPA tOEA
TRG
"H" or "L"
12/40
Semiconductor Write Cycle Function Table
RAS Falling Edge Code RWM BWM FWM RW BW LMR LCR A 0 0 1 0 0 1 1 C 0 0 0 1 1 1 1 D DQ Write Mask Write Mask Write Mask X X X X DSF WE CAS Falling Edge B DSF 0 1 X 0 1 0 1 E DQ Valid Data Column Mask X Valid Data Column Mask Write Mask Data Color Data Masked Write (New/Old) Masked Block Write (New/Old) Masked Flash Write (New/Old) Normal Write Block Write Load Mask Register Load Color Register Function
MSM548263
WRITE MASK DATA: "Low" = Mask, "High" = No Mask Column Mask Data
DQ1 - 4 DQ1 DQ2 DQ3 DQ4 Column Mask Data Column 0 (A0 = 0, A1 = 0) Column 1 (A0 = 1, A1 = 0) Column 2 (A0 = 0, A1 = 1) Column 3 (A0 = 1, A1 = 1) Low: Mask High: No Mask
13/40
Semiconductor Early Write Cycle
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
, ,, , ,,,
tCSH tCRP tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tFHR tFSR tRFH tFSC tCFH A B tCWL tWSR tRWH tRWL C tWP tWCR tWCS tWCH tMS tMH tDHR tDS tDH D E tTHS tTHH "H" or "L"
14/40
Semiconductor Late Write Cycle
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
, ,, ,, ,
tCSH tCRP tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tFHR tFSR tRFH tFSC tCFH A B tCWL tWSR tRWH tRCS tRWL C tWP tWCR tDHR tMS tMH tDS tDH D E tTHS tOEH "H" or "L"
15/40
Semiconductor Read Modify Write Cycle
tRWC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
, ,, , ,,
tCSH tCRP tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row tFHR Column tAWD tCFH tFSR tRFH tFSC A B tCWL tWSR tRWH tRCS tCWD tRWL C tCAC tWP tRWD tRAC tMS tMH tDZC tDS tDH D
Valid Data
E
tDZO
tTHS
tTHH
tOEA tOEZ
tOEH
"H" or "L"
16/40
Semiconductor Fast Page Mode Early Write Cycle
tRASP RAS tCSH tCRP CAS tRAD tRCD tAR tASR tRAH Row tASC tCAH tASC tCAH tASC tCAS tCP tPC tCAS tCP tRSH tCAS
MSM548263
tRP
Address
DSF
WE
DQ1 - 8
TRG
,, ,
tCAH Column Column Column tFHR tFSR tRFH tFSC tCFH B tFSC tCFH tFSC tCFH A B B tCWL tCWL tCWL tWSR tRWH C tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH tWP tMS tMH tDS tDH tDS tDH tDS tDH D E E E tTHS tTHH "H" or "L"
tRAL
17/40
Semiconductor Fast Page Mode Read Modify Write Cycle
tRASP RAS tCSH tCRP CAS tRAD tRCD tAR tASR tRAH tASC tCAH tASC tCAH tASC tCAS tCP tPRWC tCAS tCP tRSH tCAS
MSM548263
tRP
, , ,
tCAH Address Row Column Column Column tFHR tFSR tRFH tFSC tCFH B tFSC tCFH tFSC tCFH DSF A B B tWSR tRWH tCWL tAWD tCWD tWP tCAC tDS tCWL tAWD tCWD tWP tCAC tDS tCWL tAWD tCWD tWP tCAC tDS WE C tRCS tMS tAA tDH tAA tDH tAA tDH tMH DQ1 - 8 D
Out In Out In Out In
tRAL
tOEZ
tOEZ
tOEZ
tTHS
tTHH
tOEA
tOEA
tOEA
TRG
"H" or "L"
18/40
Semiconductor RAS Only Refresh Cycle
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
,,, , ,,,,
tCRP tRPC tASR tRAH Row tFSR tRFH Open tTHS tTHH "H" or "L"
19/40
Semiconductor CAS before RAS Refresh Cycle
tRC tRP RAS tRAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
Note:
Code CBRR CBRS CBRN
,,, , ,,,,
tRPC tCSR tCHR tRPC Inhibit Falling Transition tASR tRAH A tFSR tRFH B tWSR tRWH C tOFF Open "H" or "L"
The type of CBR operations are determined by the logic states of "A", "B" and "C". CBR Cycle Function Table
RAS Falling Edge A X B 0 1 1
C 1 0 1
Function
CBR Refresh (Reset All Options) CBR Refresh (Set STOP Address) CBR Refresh (No Reset Options)
STOP Address X
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Semiconductor Hidden Refresh Cycle
tRC tRAS RAS tRP tRAS
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
Note:
, , , ,,
tCRP tRCD tRSH tCHR tAR tRAD tRAL tASR tRAH tASC tCAH tASR tRAH Row Column A tFHR tFSR tRFH tFSC tCFH tFSR tRFH B tRCS tRRH tWSR tRWH C tCAC tAA tOFF Open Valid Data tRAC tTHS tTHH tOEA tOEZ "H" or "L"
The type of CBR operations are determined by the logic states of "A", "B" and "C".
21/40
Semiconductor Read Transfer 1
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
SC
SDQ1 - 8
QSF
,,,, ,
tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row SAM Start tFSR tRFH tWSR tRWH tASD tCSD tRSD Open tTRP tTLS tTLH tTP tSRS tSC tTSD tSCP tSCC tSC Note 2 tSIS tSCA tSIH tSZS tSCA tSOH Din Data Out tRQD tCQD tTQD Note 3 Note 3 "H" or "L"
Note 1: SE = "L" Note 2: There must be no rising transitions Note 3: QSF = "L"-- Lower SAM (0 - 255) is active QSF = "H"-- Upper SAM (256 - 511) is active 22/40
Semiconductor Read Transfer 2 (Real Time Read Transfer)
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
SC
SDQ1 - 8
QSF
,,,,
tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row SAM Start tFSR tRFH tWSR tRWH tCTH tATH Open tTRP tTLS tRTH tTP tSCC tSCP tSC tTSL tTSD tSCA tSOH tSCA tSOH Data Out Data Out Data Out Data Out tTQD Note 2 Note 2 "H" or "L"
Note 1: SE = "L" Note 2: QSF = "L"-- Lower SAM (0 - 255) is active QSF = "H"-- Upper SAM (256 - 511) is active
23/40
Semiconductor Split Read Transfer
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
SC
SDQ1 - 8
QSF
,,,,
tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row SAM Start Sj tFSR tRFH tWSR tRWH tCTH tATH tRTH Open tTLS tTLH tSTS tSCC tSCP tSC STOP i tSCA tSOH Si tSCA tSOH STOP j-1 STOP j Sj Data Out Data Out Data Out Data Out Data Out Data Out tSQD tSQD Note 2 Note 2 Note 2 "H" or "L"
Note 1: SE = "L" Note 2: QSF = "L"-- Lower SAM (0 - 255) is active QSF = "H"-- Upper SAM (256 - 511) is active Note 3: Si is the SAM start address in before SRT Note 4: STOP i and STOP j are programmable stop addresses 24/40
Semiconductor Masked Write Transfer
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
SC
SDQ1 - 8
QSF
,,,,
tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row SAM Start tFSR tRFH tWSR tRWH tMS tMH tCSD Mask Data tTLH Open tRSD tTLS tSRS tSCC tSC tSCP tSC Note 2 tSDZ tSOH tSDS tSDH tSDS tSDH Dout Dout Data In Data In tSDD tCQD tRQD Note 3 Note 3 "H" or "L"
Note 1: SE = "L" Note 2: There must be no rising transitions Note 3: QSF = "L"-- Lower SAM (0 - 255) is active QSF = "H"-- Upper SAM (256 - 511) is active 25/40
Semiconductor Masked Split Write Transfer
tRC tRAS RAS tRP
MSM548263
CAS
Address
DSF
WE
DQ1 - 8
TRG
SC
SDQ1 - 8
QSF
,,,,
tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row SAM Start Sj tFSR tRFH tWSR tRWH tMS tMH tCTH tATH Mask Data tRTH Open tTLS tTLH tSTS tSCC tSCP tSC STOP i Si STOP j-1 STOP j Sj tSDS tSDH tSDS tSDH Data In Data In Data In Data In Data In Data In tSQD tSQD Note 2 Note 2 Note 2 "H" or "L"
Note 1: SE = "L" Note 2: QSF = "L"-- Lower SAM (0 - 255) is active QSF = "H"-- Upper SAM (256 - 511) is active Note 3: Si is the SAM start address in before SWT Note 4: STOP i and STOP j are programmable stop addresses 26/40
Semiconductor Serial Read Cycle
tSEP SE tSCC tSC SC tSCA tSOH SDQ1 - 8 Data Out tSEZ Data tSCP tSEA tSCA tSOH Data tSCA tSOH Data Out
MSM548263
Data Out
Serial Write Cycle
tSEP SE
SC
SDQ1 - 8
Data In

tSCC tSWH tSWIS tSWIH tSWS tSC tSCP tSDS tSDH tSZE tSDS tSDH Data In Data In Data In "H" or "L"
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Semiconductor
MSM548263
PIN FUNCTIONS
Address Input: A0 - A8 The 18 address bits decode 8 bits of the 2,097,152 locations in the MSM548263 memory array. The address bits are multiplexed to 9 address input pins (A0 - A8) as standard DRAM. 9 row address bits are latched at the falling edge of RAS. The following 9 column address bits are latched at the falling edge of CAS. Row Address Strobe: RAS RAS is a basic RAM control signal. The RAM port is in standby mode when the RAS level is "high". As the standard DRAM's RAS signal function, RAS is the control input that latches the row address bits, and a random access cycle begins at the falling edge of RAS. In addition to the conventional RAS signal function, the level of the input signals CAS, TRG, WE and DSF at the falling edge of RAS, determines the MSM548263 operation mode. Column Address Strobe: CAS As the standard DRAM's CAS signal function, CAS is the control input signal that latches the column address input and the state of the special function input DSF to select in conjunction with the RAS control, either read/write operations or the special block write feature on the RAM port when the DSF is held "low" at the falling edge of RAS. CAS also acts as a RAM port output enable signal. Data Transfer/Output Enable: TRG TRG is also a control input signal having multiple functions. As the standard DRAM's OE signal function, TRG is used as an output enable control when TRG is "high" at the falling edge of RAS. In addition to the conventional OE signal function, a data transfer operation is started between the RAM port and the SAM port when TRG is "low" at the falling edge of RAS. Write Per Bit/Write Enable: WE WE is a control input signal having multiple functions. As the standard DRAM's WE signal function, this is used to write data into the memory on the RAM port when WE is "high" at the falling edge of RAS. In addition to the conventional WE signal function, the WE determines the write-per-bit function, when WE is "low" at the falling edge of RAS during RAM port operations. The WE also determines the direction of data transfer between the RAM and SAM. When the WE is "high" at the falling edge of RAS, the data is transferred from RAM to SAM (read transfer). When the WE is "low" at the falling edge of RAS, the data is transferred SAM to RAM (write transfer).
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Semiconductor Write Mask Data/Data Input and Output: DQ1 - DQ8
MSM548263
In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of RAS. Data is written only to high DQ pins. Data on low DQ pins is masked and internal data is retained. After that, they function as input/output pins similar to a standard DRAM. In persistent write-per-bit mode, DQ pins are don't care at the falling edge of RAS. The mask data are determined in the mask register load cycle. Serial Clock: SC SC is a main serial cycle control input signal. All operations of the SAM port are synchronized with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified serial access time tSCA from the rising edge of SC. In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register. Serial Enable: SE The SE is a serial access enable control and serial read/write control signal. In a serial read cycle, SE is used as an output control. In a serial write cycle, SE is used as a write enable control. When SE is "high", serial access is disabled. However, the serial address pointer location is still incremented when SC is clocked even when SE is "high". Special Function Input: DSF The DSF is latched at the falling edge of RAS and CAS. It allows for the selection of several RAM ports and transfer operating modes. In addition to the conventional multiport DRAM, the special functions consisting of flash write, block write, load/read color register, and split read/write transfer can be invoked. Special Function Output: QSF QSF is an output signal, which during split register mode indicates which half of the split SAM is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF "high" indicates that the upper SAM (256 - 511) is being accessed. Serial Input/Output: SDQ1 - SDQ8 Serial input/output mode is determined by the most recent read or write transfer cycle. When a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo write transfer cycle is performed, the SAM port is switched from output mode to input mode.
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Semiconductor
MSM548263
OPERATION MODES
Table-1 shows the function truth table for a listing of all available RAM ports and transter operation of MSM548263. The RAM port and data transfer operations are determined by the state of CAS, TRG, WE and DSF at the falling edge of RAS, and by the level of DSF at the falling edge of CAS. Table-1. Function Truth Table
RASO Code
CASO Address
W/IO
CAS /WEO
Write Pers.
Register Function CBR Refresh (Register Reset) CBR Refresh (Stop Register Set) CBR Refresh (No Reset) RAS Only Refresh Masked Write Transfer Masked Split Write Transfer Read Transfer Split Read Transfer Read/Write (New/Old Mask) Masked Block Write (New/Old) Masked Flash Write (New/Old) Read/Write (No Mask) Block Write (No Mask) Load Mask Register (Old Mask Set) Load Color Register
CAS TRG WE DSF DSF RASO CASO RASO
Mask W.M. WM Color
CBRR CBRS CBRN ROR MWT MSWT RT SRT RWM BWM FWM RW BW LMR LCR
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
* * * 1 0 0 0 0 1 1 1 1 1 1 1
1 0 1 * 0 0 1 1 0 0 0 1 1 1 1
0 1 1 0 0 1 0 1 0 0 1 0 0 1 1
--
*
* * * --
* * * *
* * * -- * * * *
-- -- -- -- Yes Yes -- --
Reset Reset
-- -- -- -- -- -- -- -- -- Use Use -- Use -- Load
-- STOP -- *
-- -- --
-- -- --
-- Row * * * * 0 1 * 0 1 0 1
Row TAP WM1 Row TAP WM1 Row TAP Row TAP * *
No/ Load Yes Yes -- -- Use Use -- -- No/ Load
Row Column WM1 Din,Dout Yes Row Row
Column A2c - 8c
No/ Load Yes Yes Yes No No Use Use Use -- -- No/ Load No/ Load
WM1
Column Select
Yes Yes No No -- --
*
WM1 -- * * * *
Din,Dout
Row Column Row Row Row
Column A2c - 8c
Column Select
* *
Mask Data Color Data
Set Load -- --
Notes:
1. With CBRS and SAM operations use stop register 2. After LMR, RWM, BWM, FWM and MSWT, use old mask which can be reset by CBRR. 30/40
Semiconductor
MSM548263
If the DSF is "high" at the falling edge of RAS, special functions such as split transfer, flash write, load mask register, load color register, CBRS and CBRN can be invoked. If the DSF is "low" at the falling edge of RAS and "high" at the falling edge of CAS, the block write feature can be invoked.
RAM PORT OPERATION
Extended RAM Read Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L" CAS falling edge --- DSF = "L" The MSM548263 offers an accelerated page mode cycle (EXTENDED PAGE MODE) by eliminating output disable from CAS "high", and it allows CAS precharge time (tCP) to occur without the output data becoming invalid. This new data out operates (Extended data out) as any RAM read or Page Mode Read, except data will be held valid after CAS goes "high", as long as RAS is "low". RAM Write Cycle: RAS falling edge --- TRG = CAS = "H", DSF = "L" CAS falling edge --- DSF = "L" 1) Write cycle with no mask: RAS falling edge -- WE = "H" If WE is set "low" at the falling edge of CAS after RAS goes "low", a write cycle is excuted. If WE is set "low" before the CAS falling edge, this cycle becomes an early write cycle, and all DQ pins attain high impedance. All 8 data are latched on the falling edge of CAS. If WE is set "low" after the CAS falling edge, this cycle becomes a late write cycle, and all 8 data are latched on the falling edge of WE. 2) Write cycle with mask: RAS falling edge -- WE = "L" If WE is set "low" at the falling edge of RAS, two modes of mask write can be invoked. #1 In new mask mode mask data is loaded and used. The mask data on DQ1 - DQ8 is latched into the write mask register at the falling edge of RAS. When the mask data is low, writing is inhibited into the RAM and the mask data is high, data is written into the RAM. This mask data is in effect during the RAS cycle. In page mode cycle the mask data is retained during page access. #2 If a load mask register cycle (LMR) has been performed, the mask data is not loaded from DQ pins, and the mask data stored in the mask register is persistently used. This operation is known as persistent write mask, set by LMR and reset by CBRR.
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Semiconductor Load/Read Color Register:
MSM548263 RAS falling edge --- CAS = TRG = WE = DSF = "H" CAS falling edge --- DSF = "H"
The MSM548263 is provided with an on-chip 8-bit color register for use during the flash write or block write operation. Each bit of the color register corresponds to one of the DRAM I/O blocks. The data presented on the DQi lines is subsequently latched into the color register at the falling edge of either CAS or WE whichever occurs later. The read color register cycle is activated by holding WE "high" at the falling edge of CAS, and throughout the remainder of the cycle. The data in the color register becomes valid on the DQi lines after the specified access times from RAS and TRG are satisfied. During the load/read color register cycle, the memory cells on the row address latched at the falling edge of RAS are refreshed. Load/Read Mask Register: RAS falling edge --- CAS = TRG = WE = DSF = "H" CAS falling edge --- DSF = "L"
The MSM548263 is provided with an on-chip 8-bit mask register for use during the mask write cycle, flash write cycle, block write cycle, masked write transfer, and masked split write transfer. Each bit of the mask register corresponds to one of the DRAM I/O blocks. The data presented on the DQi lines is subsequently latched into the mask register at the falling edge of either CAS or WE whichever occurs later. The read mask register cycle is activated by holding WE "high" at the falling edge of CAS, and throughout the remainder of the cycle. The data in the mask register becomes valid on the DQi lines after the specified access times from RAS and TRG are satisfied. During the load/read mask register cycle, the memory cells on the row address latched at the falling edge of RAS are refreshed. Flash Write: RAS falling edge --- CAS = TRG = DSF = "H", WE = "L" Flash write allows for the data in the color register to be written into all the memory locations of a selected row. Each bit of the color register corresponds to one of the DRAM I/O blocks. The flash write operation can be selectively controlled on an I/O basis in the same manner as the write per bit operation. The mask data is the same as that of a RAM write cycle.
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Semiconductor Block Write: RAS falling edge --- CAS = TRG = "H", DSF = "L" CAS falling edge --- DSF = "H"
MSM548263
Block write allows for the data in the color register to be written into 4 consecutive column address locations, starting from a selected column address in a selected row. The block write operation can be selectively controlled on an I/O basis, and a column mask capability is also available. During a block write cycle, the 2 least significant column address locations (A0C and A1C) are internally controlled, and only the 7 most significant column addresses (A2C - A8C) are latched at the falling edge of CAS. 1) No mask block write: WE "high" at the falling edge of RAS The data on 8 DQ pins is all cleared by the data of the color register. 2) Masked block write: WE "low" at the falling edge of RAS The mask data is the same as that of a RAM write cycle.
SAM PORT OPERATION
Single Register Mode High speed serial read or write operation can be performed through the SAM port independent of the RAM port operation, except during read/write transfer cycles. The preceding transfer operation determines the direction of data flow through the SAM port. If the preceding transfer is a read transfer, the SAM port is in the output mode. If the preceding transfer is write transfer, the SAM port is in the input mode. Serial data can be read out of the SAM after a read transfer has been performed. The data is shifted out of the SAM starting at any of the 512 bits locations. The TAP location corresponds to the column address selected at the falling edge of CAS during the read or write transfer cycle. The SAM registers are configured as a circular data register. The data is shifted out sequentially. It starts from the selected TAP location at the most significant bit (511), then wraps around to the least significant bit (0). Split Register Mode In split register mode data can be shifted into or out of one half of the SAM, while a split read or split write transfer is being performed on the other half of the SAM. Conventional (non split) read, or write transfer cycle must precede any split read or split write transfers. The split read and write transfers will not change the SAM port mode set by the preceding conventional transfer operation. In the split register mode, serial data can be shifted in or out of one of the split SAM registers, starting from any at the 256 TAP locations, excluding the last address of each split SAM the data is shifted in or out sequentially starting from the selected TAP location at the most significant bit (255 or 511) of the first split SAM, and then the SAM pointer moves to the TAP location selected for the second split SAM to shift data in or out sequentially, starts from this TAP location at the most significant bit (511 or 255), and finally wraps around to the least significant bit.
TAP 0 1 2
255 256 257
TAP
511
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Semiconductor
MSM548263
DATA TRANSFER OPERATIONS
The MSM548263 features two types of bidirectional data transfer capability between RAM and SAM. 1) Conventional (non split) transfer: 512 words by 8 bits of data can be loaded from RAM to SAM (Read transfer), or from SAM to RAM (Write transfer). 2) Split transfer: 256 words by 8 bits of data can be loaded from the lower/upper half of the RAM to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half of SAM to the lower/upper half of RAM (Split write transfer). The conventional transfer and split transfer modes are controlled by the DSF input signal. Data transfer are invoked by holding the TRG signal "low" at the falling edge of RAS. The MSM548263 supports 4 types of transfer operations: Read transfer, Split read transfer, Write transfer and Split write transfer as shown in the truth table. The type of transfer operation is determined by the state of CAS, WE and DSF latched at the falling edge of RAS. During conventional transfer operations, the SAM port is switched from input to output mode (Read transfer), or output to input mode (Write transfer). It remains unchanged during split transfer operation (Split read transfer or Split write transfer). Both RAM and SAM are divided by the most significant row address (AX8), as shown in Figure 1. Therefore, no data transfer between AX8 = 0 side RAM and AX8 = 1 side RAM can be provided through the SAM. Care must be taken if the split read transfer on AX8 = 1 side (or AX8 = 0 side) is provided after the read transfer or the split read transfer, is provided on AX8 = 0 side (or AX8 = 1 side).
Upper SAM 256 8
Array 256 256 8 Memory Array AX8 = 0
Serial Decoder
256 256 8 Memory
Upper SAM 256 8
256 256 8 Memory Array 256 256 8 Memory Array AX8 = 1
Lower SAM 256 8
SAM I/O Buffer SDQ1 - 8 Figure 1. RAM and SAM Configuration
Lower SAM 256 8
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Semiconductor Read Transfer: RAS falling edge --- CAS = WE = "H", TRG = DSF = "L"
MSM548263
Read transfer consists of loading a selected row of data from the RAM into the SAM register. A read transfer is invoked by holding CAS "high", TRG "low", WE "high", and DSF "low" at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge of TRG. When the transfer is completed, the SAM port is set into the output mode. In a read/real time read transfer cycle, the transfer of a new row of data is completed at the rising edge of TRG, and this data becomes valid on the SDQ lines after the specified access time tSCA from the rising edge of the subsequent SC cycles. The start address of the serial pointer of the SAM is determined by the column address selected at the falling edge of CAS. In a read transfer cycle (which is preceded by a write transfer cycle), SC clock must be held at a constant VIL or VIH after the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the specified delay tTSD from the rising edge of TRG. In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous row data appears on the SDQ lines until the TRG signal goes "high", and the serial access time tSCA for the following serial clock is satisfied. This feature allows for the first bit of the new row of data to appear on the serial output as soon as the last bit of the previous row has been strobed without any timing loss. To make this continuous data flow possible, the rising edge of TRG must be synchronized with RAS, CAS, and the subsequent rising edge of SC (tRTH, tCTH, and tTSL/tTSD must be satisfied). Masked Write Transfer: RAS falling edge --- CAS = "H", TRG = WE = DSF = "L" Write transfer cycle consists of loading the content of the SAM register into a selected row of the RAM. This write transfer is the same as a mask write operation in RAM, so new and persistent (old) mask mode can be supported. (Masked write transfer) If the SAM data to be transferred must first be loaded through the SAM, a Masked write transfer operation (all DQ pins "low" at falling edge of RAS) must precede the write transfer cycles. A masked write transfer is invoked by holding CAS "high", TRG "low", WE "low" and DSF "low" at the falling edge of RAS. The row address selected at the falling edge of RAS determines the RAM row address into which the data will be transferred. The column address selected at the falling edge of CAS determines the start address of the serial pointer of the SAM. After the write transfer is completed, the SDQ lines are set in the input mode so that serial data synchronized with the SC clock can be loaded. When consecutive write transfer operations are performed, new data must not be written into the serial register until the RAS cycle of the preceding write transfer is completed. Consequently, the SC clock must be held at a constant VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified delay tCSD from the falling edge of the CAS, at which time a new row of data can be written in the serial register. Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to the other address of RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer cycle (row address AX8).
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Semiconductor Split Data Transfer and QSF
MSM548263
The MSM548263 features a bidirectional split data transfer capability between the RAM and SAM. During split data transfer operation, the serial register is split into two halves which can be controlled independently. Split read or split write transfer operation can be performed to or from one half of the serial register, while serial data can be shifted into or out of the other half of the serial register. The most significant column address location (A8C) is controlled internally to determines which half of the serial register will be reloaded from the RAM. QSF is an output which indicates which half of the serial register is in an active state. QSF changes state when the last SC clock is applied to active split SAM. Split Read Transfer: RAS falling edge --- CAS = WE = DSF = "H", TRG = "L" The MSM548263 supports two types of split register operation. #1 Normal split register operation #2 Boundary split register operation using programmable SAM stops described later. Normal split read transfer consists of loading 256 words by 8 bits of data from a selected row of the split RAM into the corresponding non-active split SAM register. Serial data can be shifted out from the other half of the split SAM register simultaneously. During split read transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus eliminating timing restrictions as in the case of real time read transfers. A split read transfer can be performed after a delay of tSTS from the change of state of the QSF output is satisfied. Conventional (non-split) read transfer operation must precede split read transfer cycles.
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Semiconductor
MSM548263
Masked Split Write Transfer: RAS falling edge --- CAS = DSF = "H", TRG = WE = "L" Split write transfer consists of loading 256 words by 8 bits of data from the non-active split SAM register into a selected row of the corresponding split RAM. Serial data can be shifted into the other half of the split SAM register simultaneously. During split write transfer operation, the RAM port input clocks do not have to be synchronized with the serial clock SC, thus allowing for real time transfer. This operation is the same as a mask write operation in RAM, so new and persistent mode can be supported. A split write transfer can be performed after a delay of tSTS from the change of state of the QSF output is satisfied. A masked write transfer operation must precede split write transfer. The purpose is to switch the SAM port from output mode to input mode, and to set the initial TAP location prior to split write transfer operations. Programmable SAM Stops in Split Transfer Cycle The MSM548263 has a boundary split register operation using programmable stops. If a CBRS cycle has been performed, the split transfer cycle performs the boundary operation. Figure 2 shows an example of a boundary split register (4 stop points). The stop points define a SAM location at which the access will change from one half of the SAM to the other half (at the TAP address).
Lower SAM TAP1 0 TAP3 255 256
Upper SAM TAP2 511
S.T. (TAP2) Figure 2. Example of Boundary Split Register
S.T. (TAP3)
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Semiconductor
MSM548263
SAM Stop Set Cycle (CBRS): RAS falling edge --- CAS = "L", WE = "L", DSF = "H" SAM Stop location data (boundaries) are latched from address inputs at the falling edge of RAS. To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored. Once the CBRS is executed, the programmable SAM stop operation continues until CBRR. SAM Stop Boundary Table
Number of Stop Points 1 2 4 8 16 Address A4 1 1 1 1 0 A5 1 1 1 0 X A6 1 1 0 X X A7 1 0 X X X Size of Partition 256 128 64 32 16
Register Reset Cycle (CBRR): RAS falling edge --- CAS = "L", WE = "H", DSF = "L" A CBRR can reset the programmable SAM stop operation, and persistent mask write operation. The CBRR will take effect immediately; it doesn't require a split transfer cycle.
POWER UP
Power must be applied to the RAS and TRG input signals to pull them "high" before, or at the same time as, the VCC supply is turned on. After power-up, a pause of 200 ms minimum is required with RAS and TRG held "high". After the pause, a minimum of 8 RAS and 8 SC dummy cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer operations can begin. During the initialization period, the TRG signal must be held "high". If the internal refresh counter is used, a minimum 8 CAS before RAS cycles are required instead of 8 RAS cycles.
(NOTE) INITIAL STATE AFTER POWER UP
The initial state can not be guaranteed for various power up conditions and input signal levels. Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non Persistent Write-per-bit mode) after the initialization of the device is performed and before valid operations begin.
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Semiconductor
MSM548263
PACKAGE DIMENSIONS
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM548263
(Unit : mm)
TSOPII44/40-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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